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Optimization aspects relatively to placement of components of gate array VLSI
Volume 5, Issues 3-4 (1994), pp. 439–451
Vilius Žilevičius   Alfonsas Misevičius  

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https://doi.org/10.3233/INF-1994-53-411
Pub. online: 1 January 1994      Type: Research Article     

Published
1 January 1994

Abstract

In this paper optimization aspects relatively to circuit component placement problem for gate array VLSI are discussed. Practical and theoretical aspects of the methods of component placement are concerned as well. Effective heuristic algorithms for the initial placement and iterative placement improvement are described. An original strategy of global placement optimization is investigated. Some experimental results based on an automatic placement subsystem for gate arrays – AUTOPLACE developed at Department of Practical Informatics of Kaunas University of Technology are presented.

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Keywords
CAD VLSI placement optimization

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INFORMATICA

  • Online ISSN: 1822-8844
  • Print ISSN: 0868-4952
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