Informatica

In this paper, we present an effective performance driven placement with global routing algorithm for macro cells. Our algorithm uses a hierarchical, divide and conquer, quad-partitioning approach. The quad-partitioning routine uses the Tabu Search technique. Our algorithm uses the concept of proximity of regions to approximate the interconnection delays during the placement process. In addition, our algorithm can handle modules whose positions are fixed or are restricted to a particular subregion on the layout frame. Our experimental results indicate the superiority of our placement method in terms of quality of solution and run time when compared to Lin and Du (1990).

In this paper optimization aspects relatively to circuit component placement problem for gate array VLSI are discussed. Practical and theoretical aspects of the methods of component placement are concerned as well. Effective heuristic algorithms for the initial placement and iterative placement improvement are described. An original strategy of global placement optimization is investigated. Some experimental results based on an automatic placement subsystem for gate arrays – AUTOPLACE developed at Department of Practical Informatics of Kaunas University of Technology are presented.