In this paper optimization aspects relatively to circuit component placement problem for gate array VLSI are discussed. Practical and theoretical aspects of the methods of component placement are concerned as well. Effective heuristic algorithms for the initial placement and iterative placement improvement are described. An original strategy of global placement optimization is investigated. Some experimental results based on an automatic placement subsystem for gate arrays – AUTOPLACE developed at Department of Practical Informatics of Kaunas University of Technology are presented.