Pub. online:1 Jan 2007Type:Research ArticleOpen Access
Volume 18, Issue 1 (2007), pp. 3–26
The aim of this paper is to explore some features of the functional test generation problem, and on the basis of the gained experience, to propose a practical method for functional test generation. In the paper presented analysis of random search methods and adjacent stimuli generation allowed formulating a practical method for generating functional tests. This method incorporates the analyzed termination conditions of generation, exploits the advantages of random and deterministic search, as well as the feature that the sets of the selected input stimuli can be merged easily in order to obtain a better set of test patterns.
Pub. online:1 Jan 2003Type:Research ArticleOpen Access
Volume 14, Issue 2 (2003), pp. 135–154
Identifying legal and illegal states significantly reduces computational complexity of ATPG. A unified framework for identification of the legal and illegal states is presented. Most known methods for identification of the legal and illegal states are interpretable within this framework. New theorems and the resulting procedures for identifying exact collection of legal or illegal states of a circuit are presented. Experimental results demonstrate that exact collection of legal states for some circuits is significantly smaller than collections obtained by backward state search algorithm and by algorithm based on combinational ATPG theorems. The use of the exact collection of legal states allows identifying more undetectable faults. The proposed procedure for identifying of the exact collection of legal states starts from any state of the circuit, builds initially an enlarged collection of legal states and converges rapidly to the exact solution.
Volume 16, Issue 1 (2005), pp. 19–36
The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. In this paper we consider the realization-independent testing and the impact of circuit realization on the fault coverage. We investigated two fault models (input-output pin pair fault and input-input-output pin triplet fault) that are used by test generation for circuits described at system description level. The test generation on the system-level model is preferable if the efforts and the duration of the test supplement activities are less than the efforts and the duration of the test generation on gate-level model. The test set for the black-box model is larger as compared to the test set for the particular realization of the circuit. However, large test sets for the black-box model can be compacted by analysis not only according to the stuck-at faults, but also according to various defects for the particular realization.