The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. In this paper we consider the realization-independent testing and the impact of circuit realization on the fault coverage. We investigated two fault models (input-output pin pair fault and input-input-output pin triplet fault) that are used by test generation for circuits described at system description level. The test generation on the system-level model is preferable if the efforts and the duration of the test supplement activities are less than the efforts and the duration of the test generation on gate-level model. The test set for the black-box model is larger as compared to the test set for the particular realization of the circuit. However, large test sets for the black-box model can be compacted by analysis not only according to the stuck-at faults, but also according to various defects for the particular realization.