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<!DOCTYPE article PUBLIC "-//NLM//DTD JATS (Z39.96) Journal Publishing DTD v1.0 20120330//EN" "JATS-journalpublishing1.dtd"><article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" article-type="research-article"><front><journal-meta><journal-id journal-id-type="publisher-id">INFORMATICA</journal-id><journal-title-group><journal-title>Informatica</journal-title></journal-title-group><issn pub-type="epub">0868-4952</issn><issn pub-type="ppub">0868-4952</issn><publisher><publisher-name>VU</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="publisher-id">INF9409</article-id><article-id pub-id-type="doi">10.3233/INF-1998-9409</article-id><article-categories><subj-group subj-group-type="heading"><subject>Research article</subject></subj-group></article-categories><title-group><article-title>Design of Reusable VHDL Component Using External Functions</article-title></title-group><contrib-group><contrib contrib-type="Author"><name><surname>Štuikys</surname><given-names>Vytautas</given-names></name><email xlink:href="mailto:vytas.stuikys@if.ktu.lt">vytas.stuikys@if.ktu.lt</email><xref ref-type="aff" rid="j_INFORMATICA_aff_000"/></contrib><aff id="j_INFORMATICA_aff_000">Kaunas University of Technology, Studentų 50, 3031 Kaunas, Lithuania</aff></contrib-group><pub-date pub-type="epub"><day>01</day><month>01</month><year>1998</year></pub-date><volume>9</volume><issue>4</issue><fpage>491</fpage><lpage>506</lpage><history><date date-type="received"><day>01</day><month>02</month><year>1998</year></date></history><abstract><p>This paper describes a method how to represent and build a reusable VHDL component. By that component we can, for example, describe a family of the relative VHDL models. To represent the component, we use external functions as a mechanism to support a pre-processing and perform the instantiation of the component. A user interface, the constituent of the reusable component, serves for transferring parameters for the instantiation. We deliver a formal syntax of the functions and examples of their semantics. We describe the design of the reusable component as a procedure of transferring of: a) the intrinsic characteristics for a given family of domain objects and b) features from a given VHDL model(s). Those features require to be re-coded and extended with new ones by means of the external functions introduced. To test a reusable component, we use pre-processing and modelling.</p></abstract><kwd-group><label>Keywords</label><kwd>reusable component</kwd><kwd>template</kwd><kwd>VHDL model</kwd><kwd>pre-processing</kwd><kwd>external functions</kwd></kwd-group></article-meta></front></article>